In the integrated circuit device are fabricated a large number of circuit component elements which are coupled by a conductive pattern so that a predetermined function or functions are achieved in cooperation of the component elements, however, some of the circuit component elements such as, for example, resistors are implemented by the conductive pattern per se.
A typical example of this sort of arrangement is illustrated in FIG. 1. Reference numeral 1 designates a lightly doped p-type single crystalline silicon substrate, and a thick field oxide film 2 is grown on the silicon substrate 1, defining an active area where a component field effect transistor 3 is fabricated. The component field effect transistor 3 has a lightly-doped drain structure (which has been abbreviated as "LDD-structure"), and largely comprises heavily doped n-type source and drain regions 4 and 5, a gate structure 6 formed over that area between the heavily doped n-type source and drain regions 4 and 5, and lightly-doped n-type source and drain regions 7 and 8 extending from the heavily doped n-type source and drain regions 4 and 5. The gate structure is of a self-aligned silicide structure, and largely comprises a thin gate oxide film 9, a multiple-level gate electrode consisting of a lower polysilicon film 10 and an upper refractory metal silicide film 11, and side spacers 12 and 13 provided on both sides of the lower polysilicon film 10. The heavily doped n-type source and drain regions 4 and 5 are overlain by refractory metal silicide films 14 and 15, respectively, and the refractory metal silicide films 11, 14 and 15 aims at improvement in conductivity.
On the thick field oxide film 2 is formed an interconnection which also has a multiple-level structure. Namely, a lower polysilicon film 16 is directly formed on the thick field oxide film 2, and is overlain by a refractory metal silicide film 17. Side spacers 18 and 19 are provided on both sides of the lower polysilicon film 16, and the interconnection is merged into the gate structure 6. The interconnection is adapted to provide a large resistance and serves as a resistor 20. Thus, the polysilicon strip is partially used as the resistor 20 and partially provides the gate structure 6.
The process of fabricating the prior art structure starts with preparation of the lightly doped p-type single crystalline silicon substrate 1. The thick field oxide film 2 is thermally grown on the substrate 1 by using the localized oxidation of silicon technique, and the substrate 1 is placed in a high temperature ambience again to grow a thin silicon oxide film.
On the thin silicon oxide film is deposited a polycrystalline silicon film which is, then, patterned by using the lithographic techniques. Using the polysilicon strip thus patterned as an ion-implantation mask, n-type impurity atoms are introduced into the active area defined in the substrate 1 so that the lightly doped source and drain regions 7 and 8 are formed in the substrate 1. With the n-type impurity atoms, the polysilicon strip is lowered in resistivity.
A silicon oxide film is deposited over the entire surface of the structure, and is anisotropically etched away to form the side spacers 12, 13, 18 and 19. The thin silicon oxide film is simultaneously removed in the anisotropic etching process, and the active area between the thick field oxide film 2 and the side spacers 12 and 13 is exposed. The thin silicon oxide film left on the active area serves as the thin gate oxide film 9.
N-type impurity atoms are implanted into the exposed active area so that the heavily doped source and drain regions 4 and 5 are formed in the active area. The n-type impurity atoms are also introduced in the polysilicon strip, and the polysilicon strip is further improved in the resistivity. After the formation of the heavily doped source and drain regions 4 and 5, a conductive refractory metal is deposited over the entire surface of the structure, and the substrate is placed in a high temperature ambience. In the high temperature ambience, the conductive refractory metal reacts on the polysilicon and the single crystalline silicon, and is converted into a refractory metal silicide film. The non-reactive or residual refractory metal is etched away, and, accordingly, the refractory metal silicide films 11, 14, 15 and 17 are formed on the lower polysilicon film 10, the heavily doped source and drain regions 4 and 5 and the lower polysilicon film 16, respectively.
However, a problem is encountered in the prior art integrated circuit in that the resistor 20 occupies a large amount of area. This is because of the fact that the polysilicon strip is exposed to the ion implantation twice and overlain by the refractory metal silicide. The more impurity atoms a polysilicon strip contains, the lower resistivity it provides. Moreover, a refractory metal silicide is much smaller in resistivity than a polysilicon. The low resistive interconnection should be prolonged to provide an amount of large resistance, and, for this reason, the resistor 20 occupies a large amount of the real estate. This deteriorates the integration density, or the chip size is enlarged so as to fabricate all of the component elements.
A mask layer may provide a solution of this problem. In detail, if a photoresist mask layer is provided on the entire surface of the structure and exposes the upper refractory metal silicide film 17, the upper refractory metal silicide film 17 is selectively removed from the lower polysilicon film. However, this solution makes the process sequence complex and, accordingly, increases the production cost of the integrated circuit. Moreover, a mask pattern is liable to be improperly transferred to the photoresist film, and the resist image tends to deviate from the mask image. This results in fluctuation of resistance due to difference in geometry. The fluctuation may not be material to a digital application, however, it is serious to an analog application. The improper image transfer requests a tolerance, and, for this reason, the occupation area tends to be increased.